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Robodraw 3.0 Free Download belge scrabble conveThe present invention relates to a semiconductor device and a method of manufacturing thereof, and more specifically, to a semiconductor device having a structure in which a diffusion layer is formed on an insulating layer, and a method of manufacturing thereof.
In a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a trench structure, a conventional method of isolating an element is to form a well and a surface region of the element in one trench, and to form a diffusion layer in the well and the surface region in another trench. Since the diffusion layer is formed on a surface of the insulating layer between the trench, such a semiconductor device is called a “surface trench element”.
With the surface trench element, the area of each element region is large. Hence, the parasitic capacitance is large between the drain region and the well region, and there is a concern of increase in the on-resistance of the element. If the horizontal dimension of the surface trench element is enlarged in order to reduce the parasitic capacitance, the area of the element region is enlarged, resulting in increase in the area of an epitaxial layer, which is used for forming the substrate of the surface trench element. The area increase in the substrate decreases the fabrication yield of the element. For this reason, the surface trench element cannot satisfy the requirement for reducing the area of the element region.
As a solution to this problem, a cross-sectional structure of a trench semiconductor device with a buried diffusion layer has been proposed in Patent Document 1. In this document, the diffusion layer is formed below a surface of an insulation film, and hence, the volume of the substrate portion can be reduced.
[Patent Document 1]
Japanese Unexamined Patent Application Publication No. 2006-79668using System.Reflection;
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